16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

ADVANCE

FEATURES

· 288Mb
· 400 MHz DDR operation (800 Mb/s/pin data rate)
· Organization

- 16 Meg x 18, 32 Meg x 9 Separate I/O
- 8 banks

· Cyclic bank switching for maximum bandwidth
· Reduced cycle time (20ns at 400 MHz)
· Nonmultiplexed addresses (address multiplexing

option available)

· SRAM type interface
· Read latency (RL), row cycle time and burst

sequence length programmable

· Balanced read and write latencies in order to

optimize data bus utilization

· Data mask for WRITE commands
· Differential input clocks (CK, CK#)
· Differential input data clocks (DK, DK#)
· On-chip DLL generates CK edge-aligned data and

output data clock signals

· Data valid signal (QVLD)
· 32ms refresh (8K refresh for each bank; 64k refresh

command must be issued in total each 32ms)

· 144-ball FBGA package
· HSTL I/O (1.5V or 1.8V nominal)
· 25 ohm60 ohm matched impedance outputs
· 2.5V V

EXT

, 1.8V V

, 1.5V or 1.8V V

Q I/O

· On-die termination (ODT) R

Figure 1

144-Ball FBGA

288Mb SIO REDUCED
LATENCY (RLDRAM II)

MT49H16M18C
MT49H32M9C

OPTIONS

MARKING

· Clock Cycle Timing

2.5ns (400 MHz)

-2.5

3.3ns (300 MHz)

-3.3

5ns (200 MHz)

-5

· Configuration

16 Meg x 18

MT49H16M18CFM

32 Meg x 9

MT49H32M9CFM

· Package

144-ball, 11mm x 18.5mm FBGA

GENERAL DESCRIPTION

The Micron® 288Mb Reduced Latency DRAM

(RLDRAM) is a high-speed memory device designed for
high-bandwidth communication data storage. Applica-
tions include, but are not limited to, transmitting or
receiving buffers in telecommunication systems and data
or instruction cache applications requiring large amounts
of memory. The chip's eight-bank architecture is opti-
mized for high speed and achieves a peak bandwidth of
28.8 Gb/s using two separate 18-bit double data rate
(DDR) ports and a maximum system clock of 400 MHz.

The double data rate (DDR) separate I/O interface

transfers two 18- or 9-bit wide data word per clock cycle
at the I/O pins. The read port has dedicated data ouputs
to support READ operations, while the write port has
dedicated input pins to support WRITE operations. This
architecture eliminates the need for high-speed bus turn-
around. Output data is referenced to the free-running
output data clock.

Commands, addresses, and control signals are regis-

tered at every positive edge of the differential input clock,
while input data is registered at both positive and nega-
tive edges of the input data clock.

Read and write accesses to the RLDRAM are burst-

oriented. The burst length is programmable from 2, 4, or
8 by setting the mode register.

The device is supplied with 2.5V and 1.8V for the core

and 1.5V or 1.8V for the output drivers.

Bank scheduled refresh is supported with row ad-

dresses generated internally.

A standard FBGA 144-ball package is used to enable

ultra-high-speed data transfer rates and a simple up-
grade path from former products.

Table 1: Valid Part Numbers

PART NUMBER

DESCRIPTION

MT49H16M18CFM-xx

16 Meg x 18 RLDRAM II

MT49H32M9CFM-xx

32 Meg x 9 RLDRAM II

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

NOTE: 1. When the BL8 setting is used, A18 and A19 are "Don't Care."

When the BL4 setting is used, A19 is a "Don't Care."

Figure 2

Functional Block Diagram

16 Meg x 18

A0A19, B0, B1, B2

Column Address

Buffer

Column Address

Counter

Refresh

Counter

Row Decoder

Memory Array

Bank 1

Column Decoder

Sense Amp and Data Bus

Row Address

Buffer

Row Decoder

Memory Array

Bank 0

Column Decoder

Sense Amp and Data Bus

Row Decoder

Memory Array

Bank 2

Column Decoder

Sense Amp and Data Bus

Row Decoder

Memory Array

Bank 3

Column Decoder

Sense Amp and Data Bus

Row Decoder

Memory Array

Bank 5

Column Decoder

Sense Amp and Data Bus

Row Decoder

Memory Array

Bank 4

Column Decoder

Sense Amp and Data Bus

Row Decoder

Memory Array

Bank 6

Column Decoder

Sense Amp and Data Bus

Row Decoder

Memory Array

Bank 7

Column Decoder

DK#

WE#

CS#

REF#

REF

Sense Amp and Data Bus

Output Data Valid

QVLD

Output Data Clock

QK[1:0], QK#[1:0]

Input Buffers

Output Buffers

Control Logic and Timing Generator

D0D17

Q0Q17

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

NOTE: 1. Reserved for future use. This may optionally be connected to GND.

2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal.

This may optionally be connected to GND.

3. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal.

Figure 3

16 Meg x 18 BALL Assignment (Top View)

144-Ball FBGA

REF

EXT

TMS

TCK

(A22)

QK0#

QK0

(A21)

(A20)

QVLD

DK#

CK#

REF#

CS#

A14

A13

WE#

A16

A17

A12

A11

A10

A18

D14

Q14

A19

A15

D15

Q15

Q10

D10

QK1

QK1#

Q11

D11

D16

Q16

Q12

D12

D17

Q17

Q13

D13

REF

EXT

TDO

TDI

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 4

32 Meg x 9 Ball Assignment (Top View)

144-Ball FBGA

REF

EXT

TMS

TCK

DNU

(A22)

DNU

QK0#

QK0

(A21)

DNU

A20

DNU

QVLD

DK#

CK#

REF#

CS#

A14

A13

WE#

A16

A17

A12

A11

A10

A18

DNU

A19

A15

DNU

REF

EXT

TDO

TDI

NOTE: 1. Reserved for future use. This signal is not connected.

2. Reserved for future use. This signal is internally connected and has parasitic characteristics of a clock input signal.
3. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be

connected to GND.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Table 2: Ball Descriptions

SYMBOL

TYPE

DESCRIPTION

CK, CK#

Input

Input Clock: CK and CK# are differential clock inputs. Addresses and commands are
latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.

CS#

Input

Chip Select: CS# enables the command decoder when low and disables it when high.
When the command decoder is disabled, new commands are ignored, but internal
operations continue.

WE#, REF#

Input

Command Inputs: Sampled at the positive edge of CK, WE#, and REF# define (together
with CS#) the command to be excuted.

A[0:20]

Input

Address Inputs: A[0:20] define the row and column addresses for READ and WRITE
operations. During a MODE REGISTER SET the

address inputs define the register settings.

They are sampled at

the rising edge of CK. In the x18 configuration, A[20] is reserved for

address expansion. These expansion addresses can be treated as address inputs, but they
do not effect the operation of the device.

A21

Reserved for future use. This signal is internally connected and can be treated as an
address input.

A22

Reserved for future use. This signal is not connected and may be connected to ground.

BA[0:2]

Input

Bank Address Inputs: Select to which internal bank a command is being applied.

D0D17

Input

Data Input: The D signals form the 18-bit input data bus. During WRITE commands, data
is sampled at both edges of DK.

Q0Q17

Output

Data Output: The Q signals form the 18-bit output data bus. During READ commands,
data is referenced to both edges of QK.

QKx, QKx#

Output

Output Data Clocks: QKx and QKx# are the differential output data clocks. During READs,
they are transmitted by the RLDRAM and edge-aligned with data. QKx# is ideally 180
degrees out of phase with QKx. QK0 and QK0# are aligned with Q0Q8, QK1 and QK1#
are aligned with Q9Q17. Consult the RLDRAM II design guide for more details.

DK, DK#

Input

Input Data Clock: DK and DK# are the differential input data clocks. All input data is
referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. D0D17
are referenced to DK and DK#.

Input

Input Data Mask: The DM signal is the input mask signal for WRITE data. Input data is
masked when DM is sampled HIGH, along with the WRITE input data. DM is sampled on
both edges of DK.

QVLD

Output

Data Valid: The QVLD indicates valid output data. QVLD is edge-aligned with QKx and
QKx#.

TMS

Input

IEEE 1149.1 Test Inputs: JEDEC-standard 1.8V I/O levels. These pins may be left Not

TDI

Connected if the JTAG function is not used in the circuit

TCK

Input

IEEE 1149.1 Clock Input: JEDEC-standard 1.8V I/O levels. This pin must be tied to V

if the

JTAG function is not used in the circuit.

TDO

Output

IEEE 1149.1 Test Output: JEDEC-standard 1.8V I/O level.

Input/

External Impedance [25

W60W]: This signal is used to tune the device outputs to the

Output

system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a
resistor from this signal to ground. Connecting ZQ to GND invokes the minimum imped-
ance mode. Connecting ZQ to V

invokes the maximum impedance mode. Refer to the

Mode Register Bit Map to activate this function.

REF

Input

Input Reference Voltage: Nominally V

Q/2. Provides a reference voltage for the input

buffers.

EXT

Supply

Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Condidtions
for range.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Supply

Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions
for range.

Supply

Power Supply: Isolated Output Buffer Supply. Nominally, 1.5V or 1.8V. See DC Electrical
Characteristics and Operating Conditions for range.

Supply

Power Supply: GND.

Supply

Power Supply: Isolated Output Buffer Supply. GND

Supply

Power Supply: Isolated Termination Supply. Nominally, V

Q/2. See DC Electrical Charac-

teristics and Operating Conditions for range.

No Function: These pins may be connected to ground.

DNU

Do Not Use: These pins may be connected to ground.

Table 2: Ball Descriptions (continued)

SYMBOL

TYPE

DESCRIPTION

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

COMMANDS

According to the functional signal description, the

following command sequences are possible. All input
states or sequences not shown are illegal or reserved. All
command and address inputs must meet setup and hold
times around the rising edge of CK.

Table 3: Address Widths at Different
Burst Lengths

BURST LENGTH

x18

BL = 2

19:0

20:0

BL = 4

18:0

19:0

BL = 8

17:0

18:0

CONFIGURATION

Table 4: Command Table

OPERATION

CODE

CS#

WE#

REF#

A[20:0]

B[2:0]

NOTES

Device Deselect/No Operation

DESEL/NOP

Mode Register Set

MRS

OPCODE

Read

READ

Write

WRITE

Auto Refresh

AREF

NOTE: 1. X represents a "Don't Care"; H represents a logic HIGH; L represents a logic LOW; A represents a Valid Address; and

BA represents a Valid Bank Address.

2. Only A(17:0) are used for the MRS command.
3. See above table, Address Widths at Different Burst Lengths.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

NOTE: 1. When the chip is deselected, internal NOP commands are generated and no commands are accepted.

2. Actual refresh is 32ms/8K/8 = 0.488µs.
3. Actual refresh is 32ms/8k = 3.90µs.

Table 5: Description of Commands

COMMAND

DESCRIPTION

DESEL/NOP

The NOP command is used to perform a no operation to the RLDRAM, which essentially
deselects the chip. Use NOP commands to prevent unwanted commands from being regis-
tered during idle or wait states. Operations already in progress are not affected. Output
values depend on command history.

MRS

The mode register is set via the address inputs A(17:0). See the Mode Register Bit Map for
further information. The MRS command can only be issued when all banks are idle and no
bursts are in progress.

READ

The READ command is used to initiate a burst read access to a bank. The value on the BA(2:0)
inputs selects the bank, and the address provided on inputs A(20:0) selects the data location
within the bank.

WRITE

The WRITE command is used to initiate a burst write access to a bank. The value on the
BA(2:0) inputs selects the bank, and the address provided on inputs A(20:0) selects the data
location within the bank. Input data appearing on the DQs is written to the memory array
subject to the DM input logic level appearing coincident with the data. If the DM signal is
registered LOW, the corresponding data will be written to memory. If the DM signal is
registered HIGH, the corresponding data inputs will be ignored (i.e., this part of the data
word will not be written).

AREF

The AREF is used during normal operation of the RLDRAM to refresh the memory content of
a bank. The command is non persistent, so it must be issued each time a refresh is required.
The value on the BA(2:0) inputs selects the bank. The refresh address is generated by an
internal refresh controller, effectively making each address bit a "Don't Care" during the
AREF command. The RLDRAM requires 64K cycles at an average periodic interval of 0.49µs

(MAX). To improve efficiency, eight AREF commands (one for each bank) can be posted to
the RLDRAM at periodic intervals of 3.9µs

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

DESCRIPTION

Figure 6

Clock/Input Data Clock Command/Address Timings

CK#

CKH

CKL

CMD,

ADDR

DKx#

DKx

CKDK

DON'T CARE

DKH

DKL

VALID

Table 6: AC Electrical Characteristics

-2.5

-3.3

-5

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Clock
Clock cycle time

CK,

2.5

5.7

3.3

5.7

5.0

5.7

System frequency

CK,

175

400

175

300

175

200

MHz

Clock phase jitter

CKvar

0.30

Clock HIGH time

CKH,

DKH

0.45

0.55

0.45

0.55

0.45

0.55

Clock LOW time

CKL,

DKL

0.45

0.55

0.45

0.55

0.45

0.55

Clock to input data clock

CKDK

-0.3

0.3

-0.3

0.3

-0.3

0.3

Mode register set cycle time to any command

MRSC

Setup Times
Address/command and input setup time

AS/

0.4

0.5

0.8

Data-in and data mask to DK setup time

0.25

0.3

0.4

Hold Times
Address/command and input hold time

AH/

0.4

0.5

0.8

Data-in and data mask to DK hold time

0.25

0.3

0.4

Data and Data Strobe
Output data clock HIGH time

QKH

0.9

1.1

0.9

1.1

0.9

1.1

CKH

Output data clock LOW time

QKL

0.9

1.1

0.9

1.1

0.9

1.1

CKL

QK edge to clock edge skew

CKQK

-0.25

0.25

-0.3

0.3

-0.5

0.5

QK edge to output data edge

QKQ0,

QKQ1 -0.2

0.2

-0.25

0.25

-0.3

0.3

QK edge to data out High-Z

QKHZ

0.2

0.25

0.3

QK edge to any output data edge

QKQ

-0.3

0.3

-0.35

0.35

-0.4

0.4

QK edge to QVLD

QKVLD

-0.3

0.3

-0.35

0.35

-0.4

0.4

NOTE: 1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with

REF

of the command, address, and data signals.

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3.

QKQ0 is referenced to Q0Q8 in x18.

QKQ1 is referenced to Q9Q17 in x18.

QKQ takes into account the skew between any QKx and any Q.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

INITIALIZATION

The RLDRAM must be powered up and initialized in a

predefined manner. Operational procedures other than
those specified may result in undefined operations or
permanent damage to the device.

THE FOLLOWING SEQUENCE IS USED FOR
POWER-UP:
1. Apply power (V

EXT

, V

Q, V

REF

, V

) and start

clock as soon as the supply voltages are stable.
Apply V

and V

EXT

before or at the same time as

Q. Apply V

Q before or at the same time as

REF

and V

. Although there is no timing relation

between V

EXT

and V

, the chip starts the power-up

Figure 6

Power-Up Sequence

EXT

REF

CK#

CMD

200µs MIN

MRSC

MRS: MRS command
RFx: REFRESH Bank x
AC: Any command

2,048

cycles

MIN

6 × 2,048

cycles

MIN

MRS

RF0

RF1

RF7

DON'T CARE

ADD

1 cycle

MIN

1 cycle

MIN

sequence only after both voltages are at their
nominal levels. The pad supply must not be applied
before the core supplies. Maintain all remaining
pins in NOP conditions.

2. Maintain stable conditions for 200µs (MIN).
3. Issue three Mode Register Set commands: two

dummies plus one valid MRS.

MRSC after the valid MRS, issue eight AUTO

REFRESH commands, one on each bank and
separated by 2,048 cycles. Initial bank refresh order
does not matter.

5. After

RC, the chip is ready for normal operation.

PROGRAMMABLE IMPEDANCE
OUTPUT BUFFER

The RLDRAM II is equipped with programmable im-

pedance output buffers. This allows a user to match the
driver impedance to the system. To adjust the imped-
ance, an external precision resistor (RQ) is connected
between the ZQ pin and V

. The value of the resistor

must be five times the desired impedance. For example,
a 300

W resistor is required for an output impedance of

W. To ensure that output impedance is one-fifth the

value of RQ (within 15 percent), the range of RQ is 125

to 300

Output impedance updates may be required because,

over time, variations may occur in supply voltage and

temperature. The device samples the value of RQ.
An impedance update is transparent to the system and
does not affect device operation. All data sheet timing
and current specifications are met during an update.

CLOCK CONSIDERATIONS

The RLDRAM II utilizes internal delay-locked loops

for maximum output, data valid windows. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 cycles. Circuitry automati-
cally resets the DLL when the absence of an input clock is
detected.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Table 7: Clock Input Operating Conditions

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Clock Input Voltage Level; CK and CK#

(

)

-0.3

Q + 0.3

Clock Input Differential Voltage; CK and CK#

(

)

0.2

Q + 0.6

Clock Input Differential Voltage; CK and CK#

(

)

0.4

Q + 0.6

Clock Input Crossing Point Voltage; CK and CK#

(

)

Q/2 - 0.15

Q/2 + 0.15

NOTE: 1. DKx and DKx# have the same requirements as CK and CK#.

2. All voltages referenced to V

3. Tests for AC timing, I

, and electrical AC and DC characteristics may be conducted at nominal reference/supply

voltage levels, but the related specifications and device operations are tested for the full voltage range specified.

4. Outputs (except for I

measurements) measured with equivalent load.

5. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment, but input timing is still

referenced to V

REF

(or to the crossing point for CK/CK#), and parameter specifications are tested for the specified AC

input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is
2 V/ns in the range between V

(AC) and V

(AC).

6. The AC and DC input level specifications are as defined in the HSTL Standard (i.e., the receiver will effectively switch as

a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

7. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input

reference level for signals other than CK/CK# is V

REF

8. CK and CK# input slew rate must be

³ 2 V/ns (³4 V/ns if measured differentially).

9. V

is the magnitude of the difference between the input level on CK and the input level on CK#.

10. The value of V

is expected to equal V

Q/2 of the transmitting device and must track variations in the DC level of the

same.

11. CK and CK# must cross within this region.
12. CK and CK# must meet at least V

(DC)MIN when static and centered around V

Q/2.

13. Minimum peak-to-peak swing.

CK#

(DC) MAX

Maximum Clock Level

Minimum Clock Level

(DC) MIN

Q/2

Q/2 + 0.15

Q/2 - 0.15

(AC) MIN

(DC) MIN

(AC) MIN

(AC) MAX

(DC) MAX

(AC) MAX

Figure 7

Clock Input

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

MODE REGISTER SET COMMAND (MRS)

The mode register stores the data for controlling the

operating modes of the memory. It programs the RLDRAM
configuration, burst length, test mode, and I/O options.
During a MODE REGISTER SET command, the address
inputs A(17:0) are sampled and stored in the mode regis-
ter.

MRSC must be met before any command can be

issued to the RLDRAM. The mode register may be set at
any time during device operation. However, any pend-
ing operations are not guaranteed to successfully com-
plete. See the RLDRAM II design guide for more details.

A(17:10)

Reserved

Configuration

RLDRAM

Configuration

(default)

reserved

not valid

2 (default)

DLL enabled

DLL Reset

Burst Length

DLL Reset

Address

Mux

Address Mux

DLL reset (default)

reserved

Impedance
Matching

Impedance

Matching

Resistor

external

internal 50

(default)

NOTE: 1. Bits A(17:10) MUST be set to zero.
2. BL = 8 is not available for configuration 1.
3. ±15% temperature variation.

nonmultiplexed

(default)

address multiplexed

Address Mux

Enabled

Termination

On-Die
Termination

Disabled (default)

On-Die

Termination

Unused

Figure 11

Mode Register Bit Map

Figure 10

Mode Register Set Timing

Figure 9

Mode Register Set

CK#

CMD

MRSC

Note: MRS: MRS command; AC: Any command

MRS

NOP

DON'T CARE

CK#

WE#

REF#

A(17:0)

CS#

COD

A(20:18)

BA(2:0)

DON'T CARE

Note: COD: code to be loaded

into the register

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

CONFIGURATION TABLE

Table 8 shows, for different operating frequencies, the

different RLDRAM configurations that can be pro-
grammed into the mode register. The read and write
latency (

RL and

WL) values along with the row cycle

times (

RC) are shown in clock cycles as well as in nano-

seconds.

The shaded areas correspond to configurations that

are not allowed.

NOTE: 1. BL = 8 is not available for configuration 1.

CONFIGURATION

Table 8: RLDRAM Configuration Table

FREQUENCY

SYMBOL

UNIT

cycles

400 MHz

20.0

22.5

300 MHz

20.0

26.7

20.0

26.7

23.3

30.0

200 MHz

20.0

30.0

40.0

20.0

30.0

40.0

25.0

35.0

45.0

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

WRITE BASIC INFORMATION

Write accesses are initiated with a WRITE command,

as shown in the WRITE Command figure on the right.
Row and bank addresses are provided together with the
WRITE command.

During WRITE commands, data will be registered at

both edges of DK according to the programmed burst
length (BL). A write latency (WL) one cycle longer than
the programmed read latency (RL + 1) is present, with the
first valid data registered at the first rising DK edge WL
cycles after the WRITE command.

Any WRITE burst may be followed by a subsequent

READ command. Figures 16 and 17 illustrate the timing
requirements for a WRITE followed by a READ for bursts
of two and four, respectively.

Setup and hold time for incoming DQ relative to the

DK edges are specified as

DS and

DH. The input data is

masked if the corresponding DM signal is HIGH. The
setup and hold times for data mask are also

DS and

DH.

Figure 12

WRITE Command

Figure 13

Basic WRITE Burst/DM Timing

DK#

DON'T CARE

Write
Latency

Data
masked

CK#

CKDK

Table 9: Timing Parameters

-2.5

-3.3

-5

SYMBOL

MIN MAX

MIN MAX UNITS

0.25

0.3

0.4

0.25

0.3

0.4

CKDK

-0.3

0.3

-0.3

0.3

-0.3

0.3

CK#

WE#

REF#

CS#

A(20:0)

BA(20:0)

DON'T CARE

Note: A: address;

BA: bank address

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 14

WRITE Burst Basic Sequence: BL = 2, RL = 4, WL = 5, Configuration 1

Figure 15

WRITE Burst Basic Sequence: BL = 4, RL = 4, WL = 5, Configuration 1

NOTE:

Any free bank may be used in any given CMD. The sequence shown is only one example of a back sequence.

CK#

CMD

ADDR

WL = 5

D0a

D1a

D0b

D1b D2a D2b D3a

BA0

BA1

BA2

BA3

BA0

BA4

BA5

BA6

BA7

Note: A/BAx: address A of bank x

WR: WRITE command

Dxy: Data y to bank x

RC: row cycle time

WL: write latency

DON'T CARE

DK#

RC = 4

ADDR

BA0

BA1

BA0

BA3

BA0

CK#

CMD

WL = 5

D0a

D0c

D0b

D0d D1a D1b

D1c

NOP

Note: A/BAx: address A of bank x

WR: WRITE command

Dxy: Data y to bank x

RC: row cycle time

WL: write latency

DON'T CARE

DK#

RC = 4

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 18

READ Command

CK#

WE#

REF#

CS#

A(20:0)

BA(2:0)

DON'T CARE

Note: A: Address

BA: Bank Address

READ BASIC INFORMATION

Read accesses are initiated with a READ command, as

shown in Figure 18. Row and bank addresses are pro-
vided with the READ command.

During READ bursts, the memory device drives the

read data edge-aligned with the QK signal. After a pro-
grammable read latency, data is available at the outputs.
The data valid signal indicates that valid data will be
present in the next half clock cycle.

The skew between QK and the crossing point of CK is

specified as

CKQK.

QKQ0 is the skew between QK0 and

the last valid data edge considered over all the data
generated at the Q signals.

QKQ1 is the skew between

QK1 and the last valid data edge considered over all the
data generated at the Q signals.

QKQx is derived at each

QKx clock edge and is not cumulative over time.

QKQ is

the maximum of

QKQ0 and

QKQ1.

After completion of a burst, assuming no other com-

mands have been initiated, output data (Q) will go High-
Z. Back-to-back READ commands are possible, produc-
ing a continuous flow of output data.

The data valid window is derived from each QK

transisition and is defined as: MIN(

QKH,

QKL) -

QKQ(MAX)).

Any READ burst may be followed by a subsequent

WRITE command. Figures 22 illustrates the timing re-
quirements for a READ followed by a WRITE.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 19

Basic READ Burst Timing

QKVLD

QKQ

Note 1

QKQ

CKQK

QVLD

CK#

QKx

QKx#

CKH

CKL

QKL

QKH

UNDEFINED

-2.5

-3.3

-5

SYMBOL

MIN MAX

MIN MAX UNITS

QKQ

-0.3

0.3 -0.35 0.35 -0.4

0.4

QKQ0,

QKQ1

-0.2

0.2 -0.25 0.25 -0.3

0.3

QKVLD

-0.3

0.3 -0.35 0.35

-0.4

0.4

QKH

0.9

1.1

0.9

1.1

0.9

1.1

CKH

QKL

0.9

1.1

0.9

1.1

0.9

1.1

CKL

Table 10: Timing Parameters

-2.5

-3.3

-5

SYMBOL

MIN MAX

MIN MAX UNITS

2.5

5.7

3.3

5.7

5.0

5.7

CKH

0.45 0.55 0.45 0.55 0.45 0.55

CKL

0.45 0.55 0.45 0.55 0.45 0.55

CKQK

-0.25 0.25

-0.3

0.3

-0.5

0.5

NOTE: 1. Minimum data valid window can be expressed as MIN(

QKH,

QKL) - 2 x

QKQx(MAX).

QKQ0 is referenced to DQ0DQ8 in x18.

QKQ1 is referenced to DQ9DQ17 in x18.

QKQ takes into account the skew between any QKx and any DQ.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 24

READ/WRITE Interleave: BL = 4,

RC = 4, RL = 4, WL = 5, Configuration 1

Figure 25

READ/WRITE Interleave: BL = 4,

RC = 6, RL = 6, WL = 7, Configuration 1

ADDR

CK#

CMD

WL = 5

Q0a

Q0c

Q0b

Q0d Q2a Q2b Q2c

Q2d

Note: A/BAx: address A of bank x

WR: WRITE command

: Data y to bank x

WL: write latency

RD: READ command

Qxy: data part

from bank

RL: read latency

RC: row cycle time

QKx#

QKx

RL = 4

Q0b

Q0a

Q0c Q0d Q2a

D1a

D1c

D1b

D1d D3a D3b

D3c

D3d

D1a

RC = 4

BA0

BA1

BA2

BA3

BA0

BA1

BA2

BA3

BA0

BA1

BA2

DON'T CARE

UNDEFINED

ADDR

CK#

CMD

WL = 7

Q0a

Q0c

Q0b

Q0d Q2a Q2b Q2c Q2d

QKx#

QKx

RL = 6

Q4b

Q4a

Q4c Q4d Q2a

D1a

D1c

D1b

D1d D3a D3b D3c D3d D5a

RC = 6

BA0

BA1

BA2

BA3

BA4

BA5

BA0

BA1

BA2

BA3

BA2

Q0a Q0b Q0c Q0d

Q2a

D5c

D5b

D5d D1a

BA4

BA5

BA0

BA1

BA2

Note: A/BAx: address A of bank x

WR: WRITE command

: data y to bank x

WL: write latency

RD: READ command

Qxy: data part

from bank

RL: read latency

RC: row cycle time

DON'T CARE

UNDEFINED

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 26

READ/WRITE Interleave, BL = 4,

RC = 8, RL = 8, WL = 9, Configuration 1

WL = 9

Q0a

Q0c

Q0b

Q0d Q2a Q2b Q2c Q2d

Q4b

Q4a

Q4c Q4d Q6a

D1a

D1c

D1b

D1d D3a D3b D3c D3d D5a

BA7

BA0

BA1

BA2

BA3

BA4

BA5

BA6

BA7

BA0

BA1

ADDR

CK#

CMD

QKx#

QKx

RL = 8

RC = 8

BA0

BA1

BA2

D5c

D5b

D5d D7a D7b D7c

Q6b Q6c Q6d

Q0b

Q0a

Q0c

Note: A/BAx: address A of bank x

WR: WRITE command

: data y to bank x

WL: write latency

RD: READ command

DON'T CARE

UNDEFINED

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

AUTO REFRESH COMMAND (AREF)

AREF is used to perform a refresh cycle on one row in

a specific bank. The row addresses are generated by an
internal refresh counter for each bank; external address
pins are "DON'T CARE." The delay between the AREF
command and a subsequent command to the same bank
must be at least

RC.

Within a period of 32ms (

REF), the entire memory

must be refreshed. Figure 28 illustrates an example of a
continuous refresh sequence. Other refresh strategies,
such as burst refresh, are also possible.

Figure 27

AUTO REFRESH Command

CK#

CMD

Note: ACx: Any command on bank x

ARFx: Auto Refresh bank x

ACy: Any command on different bank

ARFx

ACy

ACx

ACy

ARFx

ACy

DON'T CARE

Figure 28

AUTO REFRESH Cycle

CK#

WE#

REF#

CS#

A(20:0)

BA(2:0)

Note: BA: bank address

NOTE:

RC is configuration-dependent. Refer to Table 8 RLDRAM Configuration on page 13.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Table 11: On-Die Termination DC Parameters

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS NOTES

Termination Voltage

0.95 x V

REF

1.05 x V

REF

1, 2

On-Die Termination

135

165

Figure 29

On-Die Termination-Equivalent Circuit

Receiver

ON DIE TERMINATION

On-die termination is enabled by setting A9 to one

during a MODE REGISTER SET (MRS) command.
With on-die termination on, all the DQs are terminated
to V

with a resistance R

. The command, address, and

clock signals are not terminated. Figure 29 shows the
equivalent circuit of a DQ receiver with on-die

termination. On-die terminations are dynamically
switched off during READ commands and are designed
to be off prior to the RLDRAM driving the bus. Similarly,
on-die terminations are designed to switch on after the
RLDRAM has issued the last piece of data.

NOTE: 1. All voltages referenced to V

(GND).

2. V

is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

3. The R

value is measured at 70°C T

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 31

READ-NOP-READ with ODT: BL = 2, Configuration 1

CK#

CMD

ADDR

RL = 4

QKx

QKx#

Q0a Q0b

Q2a Q2b

BA0

BA2

NOP

Note: A/BAx: address A of bank x

RD: READ

Dxy: data y to bank x

RL: read latency

DON'T CARE

UNDEFINED

ODT

ODT ON

QVLD

ODT ON

ODT OFF

ODT ON

Figure 32

READ-NOP-NOP-READ with ODT: BL = 2, Configuration 1

CK#

CMD

ADDR

RL = 4

QKx

QKx#

Q0a Q0b

Q2a Q2b

BA0

BA2

NOP

Note: A/BAx: address A of bank x

RD: READ

Dxy: data y to bank x

RL: read latency

DON'T CARE

UNDEFINED

ODT

ODT ON

QVLD

ODT ON

ODT OFF

ODT ON

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

OPERATION WITH MULTIPLEXED
ADDRESSES

In multiplexed address mode, the address can be

provided to the RLDRAM in two parts that are latched
into the memory with two consecutive rising clock edges.
This provides the advantage that a maximim of 11 ad-
dress pins are required to control the RLDRAM, reducing
the number of pins on the controller side. The data bus
efficiency in continuous burst mode is not affected for
BL4 and BL8 since at least two clocks are required to read
the data out of the memory. The bank addresses are
delivered to the RLDRAM at the same time as the WRITE
command and the first address part, Ax.

This option is available by setting bit A5 to '1' in the

mode register. Once this bit is set the READ, WRITE, and
MRS commands follow the format described in Figure
33. See Figure 35 for the power-up sequence.

NOTE: The minimum setup and hold times of the two address parts are defined

AS and

AH.

CK#

WE#

REF#

CS#

A<20:0>

BA<2:0>

READ

WRITE

DON'T CARE

Note: Ax, Ay: Address

BA: Bank Address

MRS

Figure 33

Command Description in Multiplexed Address Mode

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 35

Power-Up Sequence in Multiplexed Address Mode

EXT

REF

CK#

CMD

200µs MIN

MRSC

2,048 cycles

MIN

6 × 2,048

cycles MIN

MRS

RF0

RF1

RF7

DON'T CARE

ADD

MRS

MRSC

1 cycle

MIN

1 cycle

MIN

MRS: MRS command
RFx: REFRESH Bank x
AC: any command

A3x

A4x

A9y

A4y A3y A0x

Configuration

RLDRAM

Configuration

(default)

reserved

not valid

2 (default)

DLL enabled

DLL Reset

Burst Length

DLL Reset

Address

Mux

Address Mux

DLL reset (default)

reserved

Impedance
Matching

Impedance

Matching

A8x

Resistor

external

NOTE: 1. Bits A(17:11) MUST be set to zero.
2. BL = 8 is not available for configuration 1.
3. ±15% temperature variation.

A5x

nonmultiplexed

(default)

address multiplexed

A9x

Enabled

Termination

Disabled (default)

On-Die

Termination

On-Die
Termination

Unused

internal 50

(default)

Figure 34

Mode Register Set Command in Multiplexed Address Mode

The addresses A0 to A6 must be set as follows in order to activate the Mode Register in the multiplexed address mode.

The following sequence must be respected in order to power up the RLDRAM in the multiplexed address mode.

NOTE: 1. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is in normal mode of operation).

2. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is already in muxed address mode).

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Table 12: Address Mapping in Multiplexed Address Mode

ADDRESSES

DATA

BURST

WIDTH LENGTH

A10

A13

A14

A17

A18

x18

BL = 2

A10

A13

A14

A17

A18

A19

A11

A12

A16

A15

BL = 4

A10

A13

A14

A17

A18

A11

A12

A16

A15

BL = 8

A10

A13

A14

A17

A11

A12

A16

A15

BL = 2

A10

A13

A14

A17

A18

A20

A19

A11

A12

A16

A15

BL = 4

A10

A13

A14

A17

A18

A19

A11

A12

A16

A15

BL = 8

A10

A13

A14

A17

A18

A11

A12

A16

A15

ADDRESS MAPPING

The address mapping is described in Table 12 as a

function of data width and burst length.

NOTE: 1. X means "Don't Care."

2. Reserved for A20 expansion in multiplexed mode.
3. Reserved for A21 expansion in multiplexed mode.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

NOTE: 1. X means "Don't Care."

2. Reserved for A20 expansion in multiplexed mode.
3. Reserved for A21 expansion in multiplexed mode.
4. BL = 8 is not available for configuration 1.

Table 13: Configuration Table In Multiplexed Address Mode

CONFIGURATION
FREQUENCY

SYMBOL

UNIT

cycles

400 MHz

20.0

22.5

25.0

300 MHz

20.0

26.7

23.3

30.0

26.7

33.3

200 MHz

20.0

30.0

40.0

25.0

35.0

45.0

35.0

40.0

50.0

CONFIGURATION TABLE

In this mode, the read and write latencies are in-

creased by one clock cycle. The RLDRAM cycle time
remains the same, as described in Table 13.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

ADDR

CK#

CMD

AREF

DON'T CARE

AREF

BADDR

BAk

BA0

BA1

BA2

BA3

BA4

BA5

BA6

BA7

BAk

Note: AREF: auto refresh

AC: any command

Ax: first part Ax of address
Ay: second part Ay of address

BAk: bank k;

k is chosen so that

tRC is met

Figure 36

Burst Refresh Operation

REFRESH COMMAND IN MULTIPLEXED
ADDRESS MODE

Similar to other commands, the refresh command is

executed on the next rising clock edge when in the mul-
tiplexed address mode. However, since only bank ad-
dress is required, the next AREF command can be ap-

plied on the following clock. In order to comply with the
chip command processing, two clock cycles have to be
introduced between the last AREF command and any
other command as represented in Figure 36.

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Figure 37

WRITE Burst Basic Sequence: BL = 4,

with Multiplexed Addresses, Configuration 1, WL = 6

Figure 38

READ Burst Basic Sequence: BL = 4,

with Multiplexed Addresses, Configuration 1, RL = 5

CK#

CMD

ADDR

RL = 5

QKx

QKx#

Q0a

Q0c

Q0b

Q0d Q1a Q1b Q1c

NOP

Note: Ax/BAk: address Ax of bank k

Ay: address Ay of bank k

RD: READ

Qjk: data k to bank j

RL: read latency

BA1

BA2

BA0

BA3

BA1

BA2

BA0

BA3

DON'T CARE

UNDEFINED

CK#

CMD

ADDR

WL = 6

D0a

D0c

D0b

D0d D1a

BA0

BA1

BA2

BA3

BA0

NOP

Note: Ax/BAk: address Ax of bank k

Ay: address Ay of bank k

WR: WRITE

Djk: data k to bank j

WL: write latency

DON'T CARE

DK#

BA0

BA1

BA2

BA3

16 Meg x 18, 32 Meg x 9, 2.5V V

EXT

, 1.8V V

, HSTL, SIO, RLDRAM II

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT49H16M18C_3.p65 Rev. 3, Pub. 05/03

ADVANCE

16 MEG x 18, 32 MEG x 9

2.5V V

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, HSTL, SIO, RLDRAM II

IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)

RLDRAM incorporates a serial boundary scan test

access port (TAP). This port operates in accordance with
IEEE Standard 1149.1-2001. The TAP operates using
JEDEC-standard logic levels.

RLDRAM contains a TAP controller, instruction regis-

ter, boundary scan register, bypass register, and ID regis-
ter.

DISABLING THE JTAG FEATURE

It is possible to operate the RLDRAM without using

the JTAG feature. To disable the TAP controller, TCK
must be tied LOW (V

) to prevent clocking of the device.

TDI and TMS are internally pulled up and may be uncon-
nected. They may alternately be connected to V

through

a pull-up resistor. TDO should be left unconnected. Upon
power-up, the device will come up in a reset state which
will not interfere with the operation of the device.

TEST ACCESS PORT (TAP)

TEST CLOCK (TCK)

The test clock is used only with the TAP controller. All

inputs are captured on the rising edge of TCK. All outputs
are driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It is
allowable to leave this pin unconnected if the TAP is not
used. The pin is pulled up internally, resulting in a logic
HIGH level.

TEST DATA-IN (TDI)

The TDI pin is used to serially input information into

the registers and can be connected to the input of any of
the registers. The register between TDI and TDO is cho-
sen by the instruction that is loaded into the TAP instruc-
tion register. For information on loading the instruction
register, see Figure 39. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application.
TDI is connected to the most significant bit (MSB) of any
register (see Figure 40).

TEST DATA-OUT (TDO)

The TDO output pin is used to serially clock data-out

from the registers. The output is active depending upon
the current state of the TAP state machine (see Figure 39).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register
(see Figure 40).

PERFORMING A TAP RESET

A RESET is performed by forcing TMS HIGH (V

) for

five rising edges of TCK. This RESET does not affect the
operation of the RLDRAM and may be performed while
the RLDRAM is operating.

At power-up, the TAP is reset internally to ensure that

TDO comes up in a High-Z state.

Figure 39

TAP Controller State Diagram

Note: The 0/1 next to each state represents the value of

TMS at the rising edge of TCK.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register

Selection

Circuitry

Selection

Circuitry

TCK

TMS

TAP Controller

TDI

TDO

Note: x = 112 for all configurations.

Figure 40

TAP Controller Block Diagram

16 Meg x 18, 32 Meg x 9, 2.5V V

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TAP REGISTERS

Registers are connected between the TDI and TDO

pins and allow data to be scanned into and out of the
RLDRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data is
output on the TDO pin on the falling edge of TCK.

INSTRUCTION REGISTER

Eight-bit instructions can be serially loaded into the

instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in Figure
40. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as described in the previous section.

When the TAP controller is in the Capture-IR state, the

two least significant bits are loaded with a binary "01"
pattern to allow for fault isolation of the board-level serial
test data path.

BYPASS REGISTER

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain chips.
The bypass register is a single-bit register that can be
placed between the TDI and TDO pins. This allows data
to be shifted through the RLDRAM with minimal delay.
The bypass register is set LOW (V

) when the BYPASS

instruction is executed.

BOUNDARY SCAN REGISTER

The boundary scan register is connected to all the

input and bidirectional pins on the RLDRAM. Several
pins are also included in the scan register to reserved
pins. The RLDRAM has a 113-bit register.

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the
Shift-DR state.

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to one
of the pins on the RLDRAM package. The MSB of the
register is connected to TDI, and the LSB is connected to
TDO.

IDENTIFICATION (ID) REGISTER

The ID register is loaded with a vendor-specific, 32-bit

code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The
IDCODE is hardwired into the RLDRAM and can be shifted
out when the TAP controller is in the Shift-DR state. The
ID register has a vendor code and other information
described in the Identification Register Definitions table.

TAP INSTRUCTION SET

OVERVIEW

Many different (2

) instructions are possible with the

eight-bit instruction register. All used combinations are
listed in Table18, Instruction Codes. These six instruc-
tions are described in detail below. The remaining in-
structions are reserved and should not be used.

The TAP controller used in this RLDRAM is fully com-

pliant to the 1149.1 convention.

Instructions are loaded into the TAP controller during

the Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI
and TDO pins. To execute the instruction once it is shifted
in, the TAP controller needs to be moved into the Update-
IR state.

EXTEST

The EXTEST instruction allows circuitry external to

the component package to be tested. Boundary-scan
register cells at output pins are used to apply a test vector,
while those at input pins capture test results. Typically,
the first test vector to be applied using the EXTEST in-
struction will be shifted into the boundary scan register
using the PRELOAD instrucion. Thus, during the Up-
date-IR state of EXTEST, the output driver is turned on
and the PRELOAD data is driven onto the output pins.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI and
TDO pins and allows the IDCODE to be shifted out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction
register upon power-up or whenever the TAP controller
is given a test logic reset state.

HIGH Z

The HIGH Z instruction causes the boundary scan

CLAMP

When the CLAMP instruction is loaded into the in-

struction register, the data driven by the output pins are
determined from the values held in the boundary scan
register.

16 Meg x 18, 32 Meg x 9, 2.5V V

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way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ig-
nore the value of the CK and CK# captured in the bound-
ary scan register.

Once the data is captured, it is possible to shift out the

data by putting the TAP into the Shift-DR state. This places
the boundary scan register between the TDI and TDO pins.

BYPASS

When the BYPASS instruction is loaded in the instruc-

tion register and the TAP is placed in a Shift-DR state, the
bypass register is placed between TDI and TDO. The
advantage of the BYPASS instruction is that it shortens
the boundary scan path when multiple devices are con-
nected together on a board.

RESERVED

These instructions are not implemented but are re-

served for future use. Do not use these instructions.

SAMPLE/PRELOAD

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional pins is captured in the boundary scan
register.

The user must be aware that the TAP controller clock

can only operate at a frequency up to 50 MHz, while the
RLDRAM clock operates significantly faster. Because there
is a large difference between the clock frequencies, it is
possible that during the Capture-DR state, an input or
output will undergo a transition. The TAP may then try to
capture a signal while in transition (metastable state).
This will not harm the device, but there is no guarantee as
to the value that will be captured. Repeatable results may
not be possible.

To ensure that the boundary scan register will capture

the correct value of a signal, the RLDRAM signal must be
stabilized long enough to meet the TAP controller's cap-
ture setup plus hold time (

CS plus

CH). The RLDRAM

clock input might not be captured correctly if there is no

16 Meg x 18, 32 Meg x 9, 2.5V V

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TLTH

Test Clock

(TCK)

Test Mode Select

(TMS)

tTHTL

Test Data-Out

(TDO)

tTHTH

Test Data-In

(TDI)

tTHMX

tMVTH

tTHDX

tDVTH

tTLOX

tTLOV

DON'T CARE

UNDEFINED

Table 14: TAP AC Electrical Characteristics

(+0°C

£ T

£ +100°C; +1.7V £ V

£ +1.9V)

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock
Clock cycle time

THTH

Clock frequency

MHz

Clock HIGH time

THTL

Clock LOW time

TLTH

Output Times
TCK LOW to TDO unknown

TLOX

TCK LOW to TDO valid

TLOV

TDI valid to TCK HIGH

DVTH

TCK HIGH to TDI invalid

THDX

Setup Times
TMS setup

MVTH

Capture setup

Hold Times
TMS hold

THMX

Capture hold

NOTE: 1.

CS and

CH refer to the setup and hold time requirements of latching data from the boundary scan register.

Figure 41

TAP Timing

16 Meg x 18, 32 Meg x 9, 2.5V V

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Table 15: TAP DC Electrical Characteristics and Operating Conditions

(+0°C

£ T

£ 100°C; +1.7V £ V

£ +1.9V, unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

REF

+ 0.15

+ 0.3

1, 2

Input Low (Logic 0) Voltage

Q - 0.3

REF

- 0.15

1, 2

Input Leakage Current

£ V

-5.0

5.0

µA

Output Leakage Current

Output disabled,

-5.0

5.0

µA

£ V

Output Low Voltage

OLC

= 100µA

REF

- tbd

Output Low Voltage

OLT

= 2mA

REF

- tbd

Output High Voltage

OHC

| = 100µA

REF

+ tbd

Output High Voltage

OHT

| = 2mA

REF

+ tbd

NOTE: 1. All voltages referenced to V

(GND).

2. Overshoot:

(AC)

£ V

+ 0.7V for t

CK/2

Undershoot: V

(AC)

³ -0.5V for t £

CK/2

During normal operation, V

Q must not exceed V

16 Meg x 18, 32 Meg x 9, 2.5V V

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Table 18: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

Extest

0000 0000 Captures I/O ring contents. Places the boundary scan register between TDI and

TDO. This operation does not affect RLDRAM operations.

ID Code

0010 0001 Loads the ID register with the vendor ID code and places the register between

TDI and TDO. This operation does not affect RLDRAM operations.

Sample/Preload

0000 0101 Captures I/O ring contents. Places the boundary scan register between TDI and

TDO.

Clamp

0000 0111 Selects the bypass register to be connected between TDI and TDO. Data driven by

output pins are determined from values held in the boundary scan register.

High Z

0000 0011 Selects the bypass register to be connected between TDI and TDO. All ouputs are

forced into high impedance state.

Bypass

1111 1111 Places the bypass register between TDI and TDO. This operation does not affect

RLDRAM operations.

Table 16: Identification Register Definitions

INSTRUCTION FIELD

ALL DEVICES

DESCRIPTION

Revision Number

abcd

ab = die revision

(31:28)

cd = 10 for x36, 01 for x18, 00 for x9.

Device ID

00jkidef10100111

def = 000 for 288M, 001 for 576M, 010 for 1G.

(27:12)

i = 0 for common I/O, 1 for separate I/O.
jk = 00 for RLDRAM, 01 for RLDRAM II.

MICRON JEDEC ID

00000101100

Allows unique identification of RLDRAM vendor.

Code (11:1)

ID Register Presence

Indicates the presence of an ID register.

Indicator (0)

Table 17: Scan Register Sizes

BIT SIZE

Instruction

Bypass

Boundary Scan

113

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Table 19: Boundary Scan (Exit) Order

NOTE: 1. Any unused pins that are in the order will read as the logic level applied to the ball site. If left floating, a value of '0'

is returned.

R10

R11

P11

P10

N11

N10

P12

N12

M11

M10

M12

L12

L11

K11

K12

J12

J11

H11

H12

G12

G10

G11

E12

F12

F10

F11

E10

E11

BIT#

FBGA BALL

U10

U11

T10

T11

R10

BIT#

FBGA BALL

BIT#

FBGA BALL

D11

D10

C11

C10

B11

B10

100

101

102

103

104

105

106

107

108

109

110

111

112

113

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ABSOLUTE MAXIMUM RATINGS*

Storage Temperature ............................. -55°C to +150°C
I/O Voltage ...................................... -0.3V to V

Q + 0.3V

Voltage on V

EXT

Supply

Relative to V

...................................... -0.3V to +2.8V

Voltage on V

Supply

Relative to V

...................................... -0.3V to +2.1V

Voltage on V

Q Supply

Relative to V

...................................... -0.3V to +2.1V

Junction Temperature** ......................................... 110°C

Table 20: DC Electrical Characteristics and Operating Conditions

(+0°C

£ T

£ +100°C; +1.7V £ V

£ +1.9V, unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage

EXT

2.38

2.63

Supply Voltage

1.7

1.9

1, 4

Isolated Output Buffer Supply

1.4

1, 4, 5

Reference Voltage

REF

0.49 x V

0.51 x V

13, 8

Termination Voltage

0.95 x V

REF

1.05 x V

REF

9, 10

Input High (Logic 1) Voltage

REF

+ 0.1

Q + 0.3

1, 4

Input Low (Logic 0) Voltage

Q - 0.3

REF

- 0.1

1, 4

Output High Current

= V

Q/2

Q/2)

6, 7,11

(1.15 x RQ/5)

(0.85 x RQ/5)

Output Low Current

= V

Q/2

Q/2)

6, 7,11

(1.15 x RQ/5)

(0.85 x RQ/5)

Clock Input Leakage Current

£ V

-5

µA

Input Leakage Current

£ V

-5

µA

Output Leakage Current

£ V

-5

µA

Reference Voltage Current

REF

-5

µA

NOTE: 1. All voltages referenced to V

(GND).

2. Typically the value of V

REF

is expect to be 0.5 x V

Q of the transmitting device. V

REF

is expected to track variations in

3. Peak-to-peak AC noise on V

REF

must not exceed 2% V

REF

(

4. Overshoot:

(AC)

£ V

+ 0.7V for t

CK/2

Undershoot:

(AC)

³ -0.5V for t £

CK/2

During normal operation, V

Q must not exceed V

Control input signals may not have pulse widths less than

CK/2 or operate at frequencies exceeding

CK (MAX).

5. V

Q can be set to a nominal 1.5V + 0.1V or 1.8V + 0.1V supply

6. I

and I

are defined as absolute values and are measured at V

Q/2. I

flows from the device, I

flows into the

device.

7. If MRS bit A8 is 0, use RQ = 250

W in the equation in lieu of presence of an external impedance matched resistor.

8. V

REF

is expected to equal V

Q/2 of the transmitting device and to track variations in the DC level of the same. Peak-

to-peak noise (noncommon mode) on V

REF

may not exceed ±2 percent of the DC value. Thus, from V

Q/2, V

REF

allowed ±2% V

Q/2 for DC error and an additional ±2% V

Q/2 for AC noise. This measurement is to be taken at the

nearest V

REF

by-pass capacitor.

9. V

is expected to be set equal to V

REF

and must track variations in the DC level of V

REF

10. On-die termination may be selected using mode register bit 9 (see Mode Register Bit Map on page 10). A resistance

from each data input signal to the nearest V

can be enabled. R

= 150

W (± 10%) at 70°C T

11. For V

and V

, refer to the Spice Model fro the RLDRAM II Command Driver.

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect
reliability.
**Junction temperature depends upon package type, cycle
time, loading, ambient temperature, and airflow.

16 Meg x 18, 32 Meg x 9, 2.5V V

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Table 22: Capacitance

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Address/Control Input Capacitance

1.5

2.5

Input/Output Capacitance (DQ)

= 25°C; f = 1 MHz

3.0

4.0

Clock Capacitance

2.0

3.0

Table 21: AC Electrical Characteristics and Operating Conditions

(+0°C

£ T

£ +100°C; +1.7V £ V

£ +1.9V, unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS NOTES

Input High (Logic 1) Voltage

Matched Impedance Mode

REF

+ 0.2

Q + 0.2

Input Low (Logic 0) Voltage

Matched Impedance Mode

Q - 0.2

REF

- 0.2

Figure 42

Output Test Conditions

10pF

Test point

(AC) MIN

(AC) MAX

Rise Time:

2 V/ns

Fall Time:

2 V/ns

GND

SWING

Figure 43

Input Waveform

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Table 13: I

Operating Conditions and Maximum Limits

(+0°C

£ T

£ +100°C; V

= MAX, unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

-2.5

-3.3

-5

UNIT NOTES

Standby

CK = Idle

)

TBD

Current

All banks idle, no inputs toggling

EXT

)

TBD

Standby

CK = MIN, CS# = 1

)

TBD

Current

No commands

EXT

)

TBD

Incremental

BL = 2,

CK = MIN,

RC = MIN,

)

TBD

Current

1 bank active

EXT

)

TBD

Incremental

BL = 4,

CK = MIN,

RC = MIN,

)

TBD

Current

1 bank active

EXT

)

TBD

Incremental

BL = 8,

CK = MIN,

RC = MIN,

)

TBD

Current

1 bank active

EXT

)

TBD

Refresh

CK = MIN

REF

)

TBD

Current

REF

EXT

)

TBD

Operating Supply

BL = 4,

CK = MIN,

RC = MIN,

)

TBD

Current Example

4 banks interleave, address

change up to 8 times

EXT

)

TBD

during minimum

continuous data

MAX

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DATA SHEET DESIGNATION

Advance:

This data sheet contains initial descriptions of products still under development.

Figure 44

144-Ball FBGA

NOTE: 1. All dimensions in millimeters.

BALL A1 ID

17.90 CTR

0.555 ±0.050

0.39 ±0.05

0.125 ±0.025

BALL A1 ID

0.10 C

SEATING PLANE

10º TYP

0.05 MAX

10.70 CTR

11.00 ±0.10

4.40 ±0.05

5.50 ±0.05

8.80

2.40 CTR

0.80 TYP

1.00 TYP

9.25 ±0.05

8.50 ±0.05

17.00

18.50 ±0.10

144X

0.45

DIMENSIONS APPLY TO SOLDER
BALLS POST REFLOW. THE
PRE-REFLOW BALL DIAMETER IS
0.50MM ON A 0.40MM SMD BALL PAD.

BALL A12

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2%Ag

BALL A1 ID

17.90 CTR

0.555 ±0.050

0.39 ±0.05

0.125 ±0.025

BALL A1 ID

0.10 C

SEATING PLANE

10º TYP

0.05 MAX

10.70 CTR

11.00 ±0.10

4.40 ±0.05

5.50 ±0.05

8.80

2.40 CTR

0.80 TYP

1.00 TYP

9.25 ±0.05

8.50 ±0.05

17.00

18.50 ±0.10

144X

0.45

DIMENSIONS APPLY TO SOLDER
BALLS POST REFLOW. THE
PRE-REFLOW BALL DIAMETER IS
0.50MM ON A 0.40MM SMD BALL PAD.

BALL A12

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2%Ag

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. RLDRAM is a trademark of

Infineon Technologies AG in various countries, and is used by Micron under license from Infineon. RLDRAM devices comprise a new

family of products developed by Infineon and Micron. All other trademarks are the property of their respective owners.

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